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| 19-1541; Rev 0; 1/00 KIT ATION EVALU ABLE AVAIL Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers General Description Features o Ultra-High Efficiency o No Current-Sense Resistor (lossless ILIMIT) o Quick-PWM with 100ns Load-Step Response o 1% VOUT Accuracy over Line and Load o Dual-Mode Fixed 1.8V/3.3V/Adj or 2.5V/Adj Outputs o Adjustable 1V to 5.5V Output Range o 2V to 28V Battery Input Range o 200/300/420/540kHz Nominal Switching Frequency o Over/Undervoltage Protection o 1.7ms Digital Soft-Start o Drives Large Synchronous-Rectifier FETs o Power-Good Indicator MAX1715 The MAX1715 PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high-voltage batteries to generate low-voltage CPU core, I/O, and chipset RAM supplies in notebook computers. Maxim's proprietary Quick-PWMTM quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns "instant-on" response to load transients while maintaining a relatively constant switching frequency. The MAX1715 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronousrectifier MOSFETs. Single-stage buck conversion allows this device to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the +5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. The MAX1715 is intended for CPU core, chipset, DRAM, or other low-voltage supplies as low as 1V. The MAX1715 is available in a 28-pin QSOP package. For applications requiring VID compliance or DAC control of output voltage, refer to the MAX1710/MAX1711 data sheet. For a single-output version, refer to the MAX1714 data sheet. Ordering Information PART MAX1715EEI TEMP. RANGE -40C to +85C PIN-PACKAGE 28 QSOP Applications Notebook Computers CPU Core Supply Chipset/RAM Supply as Low as 1V 1.8V and 2.5V I/O Supply 5V INPUT Minimal Operating Circuit BATTERY 4.5V TO 28V VDD VCC ILIM1 ILIM2 ON1 ON2 BST1 OUTPUT1 1.8V DH1 LX1 DL1 TON BST2 DH2 LX2 DL2 PGND OUTPUT2 2.5V V+ MAX1715 Pin Configuration appears at end of data sheet. OUT1 OUT2 PGOOD SKIP REF FB1 AGND FB2 Quick-PWM is a trademark of Maxim Integrated Products. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 ABSOLUTE MAXIMUM RATINGS V+ to AGND..............................................................-0.3 to +30V VDD , VCC to AGND..................................................-0.3V to +6V PGND to AGND or VCC to VDD ...........................................0.3V PGOOD, OUT_ to AGND..........................................-0.3V to +6V ILIM_, FB_, REF, SKIP, TON, ON_ to AGND ...........................................-0.3V to (VDD + 0.3V) DL_ to PGND ..............................................-0.3V to (VDD + 0.3V) BST_ to AGND........................................................-0.3V to +36V DH1 to LX1 ...............................................-0.3V to (BST1 + 0.3V) DH2 to LX2 ...............................................-0.3V to (BST2 + 0.3V) LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V REF Short Circuit to AGND.........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 8.0mW/C above +70C).....640mW/C Operating Temperature Range ..........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, 4A components from Table 1, VCC = VDD = +5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, unless otherwise noted.) (Note 1) PARAMETER Input Voltage Range Output 1 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Output 1 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Output 2 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Output 2 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Load Regulation Error Line Regulation Error Output Voltage Range OUT_ Input Resistance FB_ Input Bias Current Soft-Start Ramp Time Battery voltage, V+ VDD, VCC V+ = 2V to 28V, SKIP = VCC, TA = +25C ILOAD = 0 to 4A V+ = 2V to 28V, SKIP = VCC, TA = 0C to +85C ILOAD = 0 to 4A V+ = 2V to 28V, SKIP = VCC, TA = +25C ILOAD = 0 to 4A V+ = 2V to 28V, SKIP = VCC, TA = 0C to +85C ILOAD = 0 to 4A ILOAD = 0 to 4A, each output VCC = 4.5V to 5.5V, V+ = 4.5V to 28V Adjustable mode, each output FB_ = AGND VOUT_ = AGND Rising edge of ON_ to full current limit TON = GND On-Time (PWM1) V+ = 24V, OUT1 = 2V TON = REF TON = open TON = VDD TON = GND On-Time (PWM2) V+ = 24V, OUT2 = 2V TON = REF TON = open TON = VDD 2 112 142 210 300 154 198 292 420 1 75k -0.1 1.7 136 173 247 353 182 234 336 484 160 205 280 407 215 270 380 550 ns ns 0.1 FB1 = OUT1 FB1 = AGND FB1 = VCC FB1 = OUT1 FB1 = AGND FB1 = VCC FB2 = OUT2 FB2 = GND FB2 = OUT2 FB2 = GND CONDITIONS MIN 2 4.5 0.99 1.782 3.267 0.985 1.773 3.250 0.99 2.475 0.985 2.463 1.00 1.8 3.3 1.00 1.8 3.3 1.00 2.5 1.00 2.5 0.4 0.2 5.5 TYP MAX 28 5.5 1.01 1.818 3.333 1.105 1.827 3.350 1.01 V 2.525 1.105 V 2.538 % % V A ms V V UNITS V _______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, 4A components from Table 1, VCC = VDD = +5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, unless otherwise noted.) (Note 1) PARAMETER Minimum Off-Time Quiescent Battery Current (V+) Quiescent Supply Current (VCC + VDD) Shutdown Supply Current (VCC + VDD) Shutdown Supply Current (V+) Reference Voltage Reference Load Regulation REF Sink Current REF Fault Lockout Voltage Overvoltage Trip Threshold Overvoltage Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Lockout Time Current-Limit Threshold (Positive Direction, Fixed) Current-Limit Threshold (Positive Direction, Adjusted) Current-Limit Threshold (Negative Direction) Current-Limit Threshold, Zero Crossing Thermal Shutdown Threshold VCC Undervoltage Lockout Threshold DH Gate Driver On-Resistance DL Gate Driver On-Resistance (pull-up) DL Gate Driver On-Resistance (pull-down) DH Gate Driver Source/Sink Current DL Gate Driver Source Current DL Gate Driver Sink Current Dead Time Logic Input High Voltage Logic Input Low Voltage FB1 and FB2 forced above the regulation point ON1 = ON2 = 0 ON1 = ON2 = 0 No external REF load IREF = 0 to 50A REF in regulation Falling edge, hysteresis = 40mV With respect to error comparator threshold FB_ forced 2% above trip threshold With respect to error comparator threshold From ON_ signal going high PGND - LX_, ILIM = VCC PGND - LX_, ILIM resistor = 100k PGND - LX_, ILIM resistor = 400k PGND - LX_, TA = +25C, ILIM = VCC PGND - LX_, SKIP = AGND Hysteresis = 10C Rising edge, hysteresis = 20mV, PWM disabled below this level BST - LX forced to 5V DL, high state DL, low state DH forced to 2.5V, BST_ - LX_ forced to 5V DL forced to 2.5V DL forced to 2.5V DL rising DH rising ON_, SKIP ON_, SKIP 2.4 0.8 4.1 1.5 1.5 0.6 1 1 3 35 26 60 10 75 40 160 -145 -5 8.5 10 1.6 10.5 1.5 70 20 100 50 200 -120 3 150 4.4 5 5 2.5 80 30 125 60 240 -95 10 13 1.98 (Note 3) CONDITIONS MIN TYP 400 25 1100 <1 <1 2 2 MAX 500 70 1600 5 5 2.02 0.01 UNITS ns A A A A V V A V % s % ms mV mV mV mV C V A A A ns V V 3 MAX1715 _______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, 4A components from Table 1, VCC = VDD = +5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, unless otherwise noted.) (Note 1) PARAMETER Logic Input Current VCC level TON Threshold Float level REF level AGND level Logic Input Current Logic Input Current PGOOD Trip Threshold PGOOD Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current TON (0 or VCC) ON_, SKIP (0 or VCC) Measured at FB_, with respect to error comparator threshold, no load Falling edge, FB_ forced 2% below PGOOD trip threshold ISINK = 1mA High state, forced to 5.5V -3 -1 -8 -5.5 1.5 0.1 0.4 1 CONDITIONS SKIP, to deactivate OVP circuitry MIN -5 VCC - 0.4 3.15 1.65 3.85 2.35 0.5 3 1 -4 A A % s V A V TYP MAX -1 UNITS mA ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, 4A components from Table 1, VCC = VDD = +5V, SKIP = AGND, V+ = 15V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER Input Voltage Range Output 1 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Output 2 Error Comparator Threshold (DC Output Voltage Accuracy) (Note 2) Battery voltage, V+ VDD, VCC FB1 = OUT1 V+ = 2V to 28V, SKIP = VCC V+ = 4.5V to 28V, SKIP = VCC FB1 = AGND FB1 = VCC FB2 = OUT2 FB2 = GND TON = GND On-Time (PWM1) V+ = 24V, OUT1 = 2V TON = REF TON = open TON = VDD TON = GND On-Time (PWM2) V+ = 24V, OUT2 = 2V TON = REF TON = open TON = VDD Minimum Off-Time (Note 3) CONDITIONS MIN 2 4.5 0.98 1.764 3.234 0.98 2.45 112 142 210 300 154 198 292 420 1.00 1.8 3.3 1.00 2.5 136 173 247 353 182 234 336 484 400 TYP MAX 28 5.5 1.02 1.836 3.372 1.02 V 2.55 160 205 280 407 215 270 380 550 500 ns ns ns V UNITS V 4 _______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, 4A components from Table 1, VCC = VDD = +5V, SKIP = AGND, V+ = 15V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER Quiescent Battery Current (V+) Quiescent Supply Current (VCC + VDD) Reference Voltage Reference Load Regulation Overvoltage Trip Threshold Output Undervoltage Threshold FB1 and FB2 forced above the regulation point No external REF load IREF = 0 to 50A With respect to error comparator threshold With respect to error comparator threshold 10 60 75 32 160 12.5 70 100 50 200 150 4.1 2.4 0.8 -5 -1 4.4 1.97 CONDITIONS MIN TYP 25 1100 2 MAX 70 1600 2.03 0.01 15 80 125 62 mV 240 C V V V mA UNITS A A V V % % mV MAX1715 Current-Limit Threshold (positive PGND - LX_, ILIM = VCC direction, fixed) Current-Limit Threshold (positive PGND - LX_, ILIM resistor = 100k direction, adjusted) PGND - LX_, ILIM resistor = 400k Thermal Shutdown Threshold VCC Undervoltage Lockout Threshold Logic Input High Voltage Logic Input Low Voltage Logic Input Current Hysteresis = 10C Rising edge, hysteresis = 20mV, PWM disabled below this level ON_, SKIP ON_, SKIP SKIP, to deactivate OVP circuitry Note 1: Specifications to -40C are guaranteed by design, and not production tested. Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP = AGND, light load) the output voltage will have DC regulation higher than the trip level by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from the 50% point at the DH pin with LX = PGND, VBST = 5V. Actual in-circuit times may differ due to MOSFET switching speeds. __________________________________________Typical Operating Characteristics (Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (1.8V, 4A COMPONENTS, SKIP = GND) MAX1715-01 EFFICIENCY vs. LOAD CURRENT (1.8V, 4A COMPONENTS, SKIP = VCC) MAX1715-02 EFFICIENCY vs. LOAD CURRENT (2.5V, 4A COMPONENTS, SKIP = GND) V+ = +7V 90 EFFICIENCY (%) MAX1715-03 100 V+ = +7V 90 EFFICIENCY (%) 100 100 80 V+ = +7V EFFICIENCY (%) 60 V+ = +12V V+ = +12V 80 V+ = +20V 80 V+ = +20V 70 V+ = +12V 40 V+ = +20V 20 70 60 0.01 0.1 1 10 LOAD CURRENT (A) 0 0.01 0.1 1 10 LOAD CURRENT (A) 60 0.01 0.1 1 10 LOAD CURRENT (A) _______________________________________________________________________________________ 5 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 _____________________________Typical Operating Characteristics (continued) (Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (2.5V, 4A COMPONENTS, SKIP = VCC) MAX1715-04 EFFICIENCY vs. LOAD CURRENT (5V, 3A COMPONENTS, SKIP = GND) MAX1715-05 EFFICIENCY vs. LOAD CURRENT (5V, 3A COMPONENTS, SKIP = VCC) V+ = +7V 80 V+ = +12V MAX1715-06 100 100 V+ = +7V 90 EFFICIENCY (%) V+ = +12V 80 V+ = +20V 100 80 EFFICIENCY (%) V+ = +7V V+ = +12V 60 V+ = +20V 40 EFFICIENCY (%) 60 V+ = +20V 40 20 70 20 0 0.01 0.1 1 10 LOAD CURRENT (A) 60 0.01 0.1 1 10 LOAD CURRENT (A) 0 0.01 0.1 1 10 LOAD CURRENT (A) EFFICIENCY vs. LOAD CURRENT (3.3V, 1.5A COMPONENTS, VIN = 5V) MAX1715-07 EFFICIENCY vs. LOAD CURRENT (1.3V, 8A COMPONENTS, SKIP = GND) MAX1715-08 EFFICIENCY vs. LOAD CURRENT (1.3V, 8A COMPONENTS, SKIP = VCC) V+ = +7V 80 V+ = +12V EFFICIENCY (%) MAX1715-9 100 SKIP = GND 80 100 100 V+ = +7V EFFICIENCY (%) EFFICIENCY (%) SKIP = VCC 60 60 V+ = +20V 40 80 V+ = +12V V+ = +20V 40 20 60 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 0.01 0.1 1 10 LOAD CURRENT (A) 20 0 0 0.01 0.1 1 10 LOAD CURRENT (A) FREQUENCY vs. LOAD CURRENT (4A COMPONENTS) MAX1715-10 FREQUENCY vs. SUPPLY VOLTAGE (4A COMPONENTS, SKIP = VCC) OUT1 300 FREQUENCY (kHz) MAX1715-11 400 OUT1, SKIP = VCC 300 FREQUENCY (kHz) OUT2, SKIP = VCC 200 OUT1, SKIP = GND 100 OUT2, SKIP = GND 0 0.01 0.1 1 400 OUT2 200 100 0 10 4 8 12 16 20 24 LOAD CURRENT (A) SUPPLY VOLTAGE (V) 6 _______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers _____________________________Typical Operating Characteristics (continued) (Circuit of Figure 1, components from Table 1, VIN = +15V, SKIP = AGND, TON = unconnected, TA = +25C, unless otherwise noted.) FREQUENCY vs. TEMPERATURE (2.5V, 4A COMPONENTS, SKIP = HIGH) MAX1715-12 MAX1715 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (OUT1 = 1.8V, 4A COMPONENTS; OUT2 = 2.5V, 4A COMPONENTS; SKIP = GND) MAX1715-13 250 FREQUENCY (kHz) 200 150 100 50 0 -40 -20 0 20 40 60 600 SUPPLY CURRENT (A) 500 400 300 200 100 0 ICC 10 SUPPLY CURRENT (mA) 8 6 4 2 0 IIN IDD IDD IBATT 0 5 10 15 20 25 30 ICC 0 5 10 15 20 25 30 80 TEMPERATURE (C) INPUT VOLTAGE (V) INPUT VOLTAGE (V) LOAD-TRANSIENT RESPONSE (2.5V, 4A COMPONENTS, SKIP = GND) MAX1715-15 START-UP WAVEFORM (2.5V, 4A COMPONENTS, ACTIVE LOAD) MAX1715-16 LOAD-TRANSIENT RESPONSE (1.3V, 8A COMPONENTS, SKIP = GND) A MAX1715-17 A A B B C A = VOUT, AC-COUPLED, 100mV/div B = INDUCTOR CURRENT, 2A/div C = DL, 10V/div B C A = VOUT, 2V/div B = INDUCTOR CURRENT, 2A/div C = DL, 10V/div C A = VOUT, AC-COUPLED, 100mV/div B = INDUCTOR CURRENT, 5A/div C = DL, 10V/div OUTPUT OVERLOAD WAVEFORM (2.5V, 4A COMPONENTS, SKIP = GND) MAX1715-18 SHUTDOWN WAVEFORM (2.5V, 4A COMPONENTS, SKIP = GND) MAX1715-19 A B A B C A = VOUT, 2V/div B = INDUCTOR CURRENT, 5A/div C = DL, 10V/div C A = VOUT, 2V/div B = INDUCTOR CURRENT, 5A/div C = DL, 10V/div _______________________________________________________________________________________ MAX1715-14 300 700 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (OUT1 = 1.8V, 4A COMPONENTS; OUT2 = 2.5V, 4A COMPONENTS; SKIP = VCC) 12 7 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 Pin Description PIN 1 NAME OUT1 FUNCTION Output Voltage Connection for the OUT1 PWM. Connect directly to the junction of the external inductor and output filter capacitors. OUT1 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. Feedback Input for OUT1. Connect to AGND for 1.8V fixed output or to VCC for 3.3V fixed output, or connect to a resistor-divider from OUT1 for an adjustable output. Current-Limit Threshold Adjustment for OUT1. The LX1-PGND current-limit threshold defaults to +100mV if ILIM1 is connected to VCC. Or, connect an external resistor to AGND to adjust the limit. A precision 5A pull-up current through REXT sets the threshold from 50mV to 200mV. The voltage on the pin is 10 times the currentlimit voltage. Choose REXT equal to 2k per mV of current-limit threshold (100k to 400k). Battery Voltage Sense Connection. Connect to the input power source. V+ is used only to set the PWM oneshot timing. On-Time Selection Control Input. This is a four-level input used to determine DH_ on-time. The TON table below is for VIN = 24V, VOUT1 = 1.8V, VOUT2 = 2.5V condition. 5 TON TON AGND REF Open VCC Frequency (OUT1) (kHz) 620 485 345 235 Frequency (OUT2) (kHz) 460 355 255 170 2 FB1 3 ILIM1 4 V+ 170 6 7 8 9 10 11 SKIP PGOOD AGND REF ON1 ON2 Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connect to AGND to enable pulse-skipping operation. Power-Good Open-Drain Output. PGOOD is low when either FB_ input is more than 5.5% below the normal regulation point (typ). Analog Ground +2.0V Reference Voltage Connection. Bypass to AGND with 0.22F (min) capacitor. Can supply 50A for external loads. OUT1 ON/OFF Control Input. Drive to AGND to turn OUT1 off. Drive to VCC to turn OUT1 on. OUT2 ON/OFF Control Input. Drive to AGND to turn OUT2 off. Drive to VCC to turn OUT2 on. Current-Limit Threshold Adjustment for OUT2. The LX2-PGND current-limit threshold defaults to +100mV if ILIM2 is connected to VCC. Or, connect an external resistor to AGND to adjust the limit. A precision 5A pull-up current through REXT sets the threshold from 50mV to 200mV. The voltage on the pin is 10 times the currentlimit voltage. Choose REXT equal to 2k per mV of current-limit threshold (100k to 400k). Feedback Input for OUT2. Connect to AGND for 2.5V fixed output, or connect to a resistor-divider from OUT2 for an adjustable output. Output Voltage Connection for the OUT2 PWM. Connect directly to the junction of the external inductor and output filter capacitors. OUT2 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output mode. No Connection. These pins are not connected to any internal circuitry. Connect the N.C. pins to the ground plane to enhance thermal conductivity. 12 ILIM2 13 FB2 14 15, 23, 28 OUT2 N.C. 8 _______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers Pin Description (continued) PIN 16 17 18 19 20 21 22 24 25 26 27 NAME LX2 DH2 BST2 DL2 VDD VCC PGND DL1 BST1 DH1 LX1 FUNCTION External Inductor Connection for OUT2. Connect to the switched side of the inductor. LX2 serves as the lower supply voltage rail for the DH2 high-side gate driver and is the positive input to the OUT2 current-limit comparator. High-Side Gate Driver Output for OUT2. Swings from LX2 to BST2. Boost Flying Capacitor Connection for OUT2. Connect to an external capacitor and diode according to the Standard Application Circuit (Figure 1). See MOSFET Gate Drivers (DH_, DL_) section. Low-Side Gate-Driver Output for OUT2. DL2 swings from PGND to VDD. Supply Input for the DL Gate Drivers. Connect to the system supply voltage, +4.5V to +5.5V. Bypass to PGND with a minimum 4.7F ceramic capacitor. Analog-Supply Input. Connect to the system supply voltage, +4.5V to +5.5V, with a 20 series resistor. Bypass to AGND with a 1F ceramic capacitor. Power Ground. Connect directly to the low-side MOSFETs' sources. Serves as the negative input of the current-sense amplifiers. Low-Side Gate Driver Output for OUT1. DL1 swings PGND to VDD. Boost Flying Capacitor Connection for OUT1. Connect to an external capacitor and diode according to the Standard Application Circuit (Figure 1). See MOSFET Gate Drivers (DH_, DL_) section. High-Side Gate Driver Output for OUT1. Swings from LX1 to BST1. External Inductor Connection for OUT1. Connect to the switched side of the inductor. LX1 serves as the lower supply voltage rail for the DH1 high-side gate driver. MAX1715 _______________________________________________________________________________________ 9 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 Standard Application Circuit The standard application circuit (Figure 1) generates two low-voltage rails for general-purpose use in notebook computers (I/O supply, fixed CPU core supply, DRAM supply). This DC-DC converter steps down a battery or AC adapter voltage to voltages from 1.0V to 5.5V with high efficiency and accuracy. See Table 1 for a list of components for common applications. Table 2 lists component manufacturers. over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. Detailed Description The MAX1715 buck controller is designed for low-voltage power supplies for notebook computers. Maxim's proprietary Quick-PWM pulse-width modulator in the MAX1715 (Figure 2) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point +5V Bias Supply (VCC and VDD) The MAX1715 requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V supply can be generated with an external linear regulator such as the MAX1615. VDD = 5V BIAS SUPPLY C9 4.7F C8 1F D3 CMPSH-3A VIN 4.5V TO 28V R1 20 4 20 21 VDD VCC ILIM1 ILIM2 ON1 C1 25 N1 L1 D1 C5 0.1F N2 26 27 24 5 1 9 C7 0.22F 2 8 BST1 DH1 LX1 DL1 TON OUT1 REF FB1 AGND MAX1715 BST2 DH2 LX2 DL2 PGND OUT2 SKIP FB2 PGOOD 18 17 16 19 22 14 6 13 7 +5V 100k C6 0.1F N4 N3 V+ ON1 ON2 10 11 C11 1F 3 12 ON/OFF CONTROLS C2 OUTPUT1 1.8V C3 L2 D2 OUTPUT2 2.5V C4 POWER-GOOD INDICATOR PINS 15, 23, 28 = N.C. Figure 1. Standard Application Circuit 10 ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers Table 1. Component Selection for Standard Applications COMPONENT Input Range Frequency 2.5V at 4A 7V to 20V 255kHz MAX1715 1.8V at 4A 7V to 20V 345kHz Fairchild Semiconductor 1/2 FDS6982A Fairchild Semiconductor 1/2 FDS6982A Nihon EP10QY03 3.1H Sumida CDRH125 10F, 25V Taiyo Yuden TMK432BJ106KM 5V at 3A 7V to 20V 255kHz Fairchild Semiconductor 1/2 FDS6990A Fairchild Semiconductor 1/2 FDS6990A Nihon EP10QY03 6.8H Coiltronics UP2B 10F, 25V Taiyo Yuden TMK432BJ106KM 1.3V at 8A 7V to 20V 255kHz International Rectifier IRF7811 Fairchild Semiconductor FDS6670A Motorola MBRS340T3 1.5H Sumida CEP125-1R5MC (2) 10F, 25V Taiyo Yuden TMK432BJ106KM 3.3V at 1.5A 4.75V to 5.5V 600kHz International Rectifier 1/2 IRF7301 International Rectifier 1/2 IRF7301 -- 3.3H TOKO D73LC 100F, 10V Sanyo POSCAP 10TPA100M Fairchild Q1 High-Side MOSFET Semiconductor 1/2 FDS6982A Fairchild Q2 Low-Side MOSFET Semiconductor 1/2 FDS6982A D2 Rectifier Nihon EP10QY03 4.4H Sumida CDRH125 10F, 25V Taiyo Yuden TMK432BJ106KM L1 Inductor C1 Input Capacitor C2 Output Capacitor 330F, 6V AVX 470F, 4V Sanyo 470F, 4V Sanyo TPSV337M006R POSCAP 4TPB470M POSCAP 4TPB470M 0060 (2) 470F, 6V Kemet 100F, 10V Sanyo POSCAP T510X477108M0 10TPA100M 06AS Table 2. Component Suppliers MANUFACTURER AVX Central Semiconductor Coilcraft Coiltronics Fairchild Semiconductor International Rectifier Kemet Matsuo Motorola Murata NIEC (Nihon) Sanyo Siliconix Sprague Sumida Taiyo Yuden TDK TOKO *Distributor USA PHONE 803-946-0690 516-435-1110 847-639-6400 561-241-7876 408-822-2181 310-322-3331 408-986-0424 714-969-2491 602-303-5454 814-237-1431 800-831-9172 805-867-2555* 619-661-6835 408-988-8000 800-554-5565 603-224-1961 847-956-0666 408-573-4150 847-390-4461 800-PIK-TOKO FACTORY FAX [Country Code] [1] 803-626-3123 [1] 516-435-1824 [1] 847-639-1469 [1] 561-241-9339 [1] 408-721-1635 [1] 310-322-3332 [1] 408-986-1442 [1] 714-960-6492 [1] 602-994-6430 [1] 814-238-0490 [81] 3-3494-7414 [81] 7-2070-1174 [1] 408-970-3950 [1] 603-224-1430 [81] 3-3607-5144 [1] 408-573-4159 [1] 847-390-4405 [1] 708-699-1194 The power input and +5V bias inputs can be connected together if the input source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (ON1, ON2) must be delayed until the battery voltage is present to ensure start-up. The +5V bias supply must provide VCC and gate-drive power, so the maximum current drawn is: IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ) where ICC is 1mA typical, f is the switching frequency, and QG1 and QG2 are the MOSFET data sheet total gate-charge specification limits at VGS = 5V. Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time current-mode type with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor's ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the ______________________________________________________________________________________ 11 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 V+ BATTERY 4.5V TO 28V VDD 5V INPUT V+ VDD VDD VCC 5A ILIM_ V+ VCC 5A ILIM_ VDD 9R BST1 9R R BST2 V+ R MAX1715 PWM CONTROLLER (SEE FIGURE 3) PWM CONTROLLER (SEE FIGURE 3) DH1 CURRENT LIMIT LX1 OUTPUT1 1.8V VDD DL1 ZERO CROSSING CURRENT LIMIT DH2 LX2 ZERO CROSSING VDD DL2 PGND OUTPUT2 2.5V OUT1 FB1 OUT2 FB2 VCC 20 2V REF REF VDD SKIP TON ON1 ON2 PGOOD AGND Figure 2. Functional Diagram current-limit threshold, and the minimum off-time oneshot has timed out. On-Time One-Shot (TON) The heart of the PWM core is the one-shot that sets the high-side switch on-time for both controllers. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ 12 input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-times for side 1 are set 15% higher than the ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 IN 2V TO 28V V+ TOFF TON ON-TIME COMPUTE FROM OUT 1-SHOT TRIG Q TON TRIG 1-SHOT FROM ILIM COMPARATOR REF Q S R Q TO DH DRIVER ERROR AMP TO DL DRIVER S Q FROM ZERO-CROSSING COMPARATOR R REF -6% REF +12% REF -30% x2 OUT_ FEEDBACK MUX (SEE FIGURE 9) S2 Q TO PGOOD OR GATE OVP/UVLO LATCH TIMER S1 FB_ Figure 3. PWM Controller (one side only) Table 3. Operating Mode Truth Table ON1 0 0 1 X 1 ON2 0 1 0 X 1 SKIP X X X <-0.3V VDD MODE COMMENTS SHUTDOWN Low-power shutdown state. DL = VDD. Clears fault latches. OUT1 Disable Disable OUT1. DL1 = VDD. Clears OUT1 fault latches. OUT2 Disable Disable OUT2. DL2 = VDD. Clears OUT2 fault latches. No Fault RUN (PWM) Low Noise RUN (PFM/PWM) Disables the output overvoltage and undervoltage fault circuitry. Low-Noise operation with no automatic PWM/PFM switchover. Fixed-frequency PWM action is forced regardless of load. Inductor current reverses at light load levels. IDD draw <1.5mA (typ) plus gate-drive current. Normal operation with automatic PWM/PFM switchover for pulse-skipping at light loads. IDD <1.5mA (typ) plus gate drive current. 1 1 AGND X = Don't care ______________________________________________________________________________________ 13 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 Table 4. Frequency Selection Guidelines NOMINAL FREQUENCY (kHz) 200 300 TYPICAL APPLICATION COMMENTS Table 5. Approximate K-Factor Errors APPROX TON K-FACTOR SETTING ERROR (%) VCC OPEN REF GND 10 10 12.5 12.5 MIN VIN AT VOUT = 2V (V) 2.6 2.9 3.2 3.6 SIDE 1 K FACTOR (s) 4.24 2.96 2.08 1.63 SIDE 2 K FACTOR (s) 5.81 4.03 2.81 2.18 4-cell Li+ notebook 4-cell Li+ notebook Use for absolute best efficiency. Considered mainstream by current standards. Useful in 3-cell systems for lighter loads than the CPU core or where size is key. Good operating point for compound buck designs or desktop circuits. 420 3-cell Li+ notebook For loads above the critical conduction point, the actual switching frequency is: f= VOUT + VDROP1 t ON (VIN + VDROP2 ) 540 +5V input nominal frequency setting (200kHz, 300kHz, 420kHz, or 540kHz), while the on-times for side 2 are set 15% lower than nominal. This is done to prevent audio-frequency "beating" between the two sides, which switch asynchronously for each side: On-Time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate for the expected drop across the low-side MOSFET switch. One-shot timing error increases for the shorter on-time settings due to fixed propagation delays; it is approximately 12.5% at 540kHz and 420kHz nominal settings and 10% at the two slower settings. This translates to reduced switching-frequency accuracy at higher frequencies (Table 5). Switching frequency increases as a function of load current due to the increasing drop across the low-side MOSFET, which causes a faster inductor-current discharge ramp. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external high-side power MOSFET. Two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and PC board resistance) and the dead-time effect. These effects are the largest contributors to the change of frequency with changing load current. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. It occurs only in PWM mode (SKIP = high) when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. 14 where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path; and tON is the on-time calculated by the MAX1715. Automatic Pulse-Skipping Switchover In skip mode (SKIP low), an inherent automatic switchover to PFM takes place at light loads. This switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the "critical conduction" point). For a battery range of 7V to 24V, this threshold is relatively constant, with only a minor dependence on battery voltage. I LOAD(SKIP) K VOUT_ VIN - VOUT 2L VIN where K is the on-time scale factor (Table 5). The loadcurrent level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). For example, in the standard application circuit with VOUT1 = 2.5V, VIN = 15V, and K = 2.96s (see Table 5), switchover to pulse-skipping operation occurs at ILOAD = 0.7A or about 1/6 full load. The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 i t INDUCTOR CURRENT = VBATT -VOUT L -IPEAK -IPEAK ILOAD INDUCTOR CURRENT ILOAD = IPEAK/2 ILIMIT 0 ON-TIME TIME 0 TIME Figure 4. Pulse-Skipping/Discontinuous Crossover Point Figure 5. ``Valley'' Current-Limit Threshold Point operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). DC output accuracy specifications refer to the trip level of the error. When the inductor is in continuous conduction, the output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP = AGND, light-loaded), the output voltage will have a DC regulation higher than the trip level by approximately 1.5% due to slope compensation. Current-Limit Circuit (ILIM) The current-limit circuit employs a unique "valley" currentsensing algorithm that uses the on-state resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with internal 5A current source and an external resistor at ILIM. The current-limit threshold adjustment range is from 50mV to 200mV, corresponding to resistor values of 100k to 400k. In the adjustable mode, the current-limit threshold voltage is precisely 1/10 the voltage seen at ILIM. The threshold defaults to 100mV when ILIM is connected to VCC. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see Design Procedure). Carefully observe the PC board layout guidelines to ensure that noise and DC errors don't corrupt the current-sense signals seen by LX and PGND. Mount or 15 S Forced-PWM Mode (SKIP = high) The low-noise, forced-PWM mode (SKIP = high) disables the zero-crossing comparator, which controls the low-side switch on-time. This causes the low-side gatedrive waveform to become the complement of the highside gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop strives to maintain a duty ratio of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the noload battery current can be 10mA to 40mA, depending on the external MOSFETs. Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback transformer or coupled inductor. ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 +5V POR, UVLO, and Soft-Start VIN BST 5 DH LX MAX1715 Figure 6. Reducing the Switching-Node Rise Time place the IC close to the low-side MOSFET with short, direct traces, making a Kelvin sense connection to the source and drain terminals. Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter and preparing the PWM for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high (to enforce output overvoltage protection) until V CC rises above 4.2V, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. The ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after 1.7ms 50%. A continuously adjustable analog soft-start function can be realized by adding a capacitor in parallel with the ILIM external resistor. This soft-start method requires a minimum interval between power-down and power-up to discharge the capacitor. Power-Good Output (PGOOD) The output voltage is continuously monitored for undervoltage by the PGOOD comparator. In shutdown, softstart, and standby modes, PGOOD is actively held low. After digital soft-start has terminated, PGOOD is released if both the outputs are within 5.5% of the error comparator threshold. The PGOOD output is a true open-drain type with no parasitic ESD diodes. Note that the PGOOD undervoltage detector is completely independent of the output UVP fault detector. MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderate-size, high-side and larger, low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VBATT - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1715 will interpret the MOSFET gate as "off" while there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1 inch from the MAX1715). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay. The internal pull-down transistor that drives DL low is robust, with a 0.5 typical on-resistance. This helps prevent DL from being pulled up during the fast risetime of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronousrectifier MOSFET. However, for high-current applications, you might still encounter some combinations of high- and low-side FETs that will cause excessive gatedrain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BST, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 6). Output Overvoltage Protection (OVP) The overvoltage protection circuit is designed to protect against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The output voltage is continuously monitored for overvoltage. If the output is more than 10.5% above the trip level of the error amplifier, OVP is triggered and the circuit shuts down. The DL low-side gate-driver output is then latched high until SHDN is toggled or VCC power is cycled below 1V. This action turns on the synchronousrectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. DL is also kept high continuously when VCC UVLO is active, as well as in shutdown mode (Table 3). Note that DL latching high causes the output voltage to go slightly negative, due to energy stored in the output LC at the instant OVP activates. If the load can't tolerate being forced to a negative voltage, it may be desirable to place a power Schottky diode across the output to act as a reverse-polarity clamp (Figure 1). 16 ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 Overvoltage protection can be defeated through the SKIP test mode (Table 3). __________________Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) Input voltage range. The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum load current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) * 80%. 3) Switching frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical (Table 4). 4) Inductor operating point. This choice provides trade-offs between size vs. efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The MAX1715's pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the loadcurrent value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current. Output Undervoltage Protection (UVP) The output undervoltage protection function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1715 output voltage is under 70% of the nominal value 20ms after coming out of shutdown, the PWM is latched off and won't restart until VCC power is cycled or SHDN is toggled. No-Fault Test Mode The over/undervoltage protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to totally disable the OVP, UVP, and thermal shutdown features, and clear the fault latch if it has been set. The PWM operates as if SKIP were grounded (PFM/PWM mode). The no-fault test mode is entered by sinking 1.5mA from SKIP through an external negative voltage source in series with a resistor (Figure 7). SKIP is clamped to AGND with a silicon diode, so choose the resistor value equal to (VFORCE - 0.65V) / 1.5mA. MAX1715 SKIP APPROXIMATELY -0.65V 1.5mA VFORCE AGND Figure 7. Disabling Over/Undervoltage Protection (Test Mode) ______________________________________________________________________________________ 17 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time: VSAG = where DUTY = K (VOUT + 0.075V) VIN K (VOUT + 0.075V) VOUT + min off - time 2 CF DUTY (VIN(MIN) - VOUT ) (I LOAD(MAX) )2 L ture. A good general rule is to allow 0.5% additional resistance for each C of temperature rise. Examining the 8A circuit example with a maximum RDS(ON) = 12m at high temperature reveals the following: ILIMIT(LOW) = 90mV / 12m = 7.5A 7.5A is greater than the valley current of 6.6A, so the circuit can easily deliver the full-rated 8A using the default 100mV nominal ILIM threshold. Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the overvoltage protection circuit. In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VDIP RESR I LOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple: RESR Vp - p LIR I LOAD(MAX) where minimum off-time = 400ns typ (see Table 5). Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows: VOUT (VIN - VOUT ) L= VIN f LIR I LOAD(MAX) Example: ILOAD(MAX) = 8A, VIN = 7V, VOUT = 1.6V, f = 300kHz, 35% ripple current or LIR = 0.35: L= 1.6V (7 - 1 6) = 1.6H 7 300kHz 0.33 8A Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice; although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + [(LIR / 2) * ILOAD(MAX)] Determining the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore: ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) ILOAD(MAX) where ILIMIT(LOW) = minimum current-limit threshold voltage divided by the R DS(ON) of Q2. For the MAX1715, the minimum current-limit threshold (100mV default setting) is 90mV. Use the worst-case maximum value for RDS(ON) from the MOSFET Q2 data sheet, and add some margin for the rise in RDS(ON) with tempera- The actual microfarad capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Also, the capacitance must be great enough to prevent the inductor's stored energy from launching the output above the overvoltage protection threshold. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG equation in the Design Procedure). 18 ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers The amount of overshoot due to stored inductor energy can be calculated as: 2 LI V PEAK 2CVOUT where IPEAK is the peak inductor current. Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the MAX1715 EV kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Don't allow more than one cycle of ringing after the initial step-response under- or overshoot. MAX1715 Output Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation: f ESR = where: f ESR = f Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power up surge currents. V OUT VIN - VOUT I RMS = ILOAD VIN 2 1 RESR CF For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 15kHz. In the design example used for inductor selection, the ESR needed to support 50mVp-p ripple is 50mV/3.5A = 14.2m. Three 470F/4V Kemet T510 low-ESR tantalum capacitors in parallel provide 15m max ESR. Their typical combined ESR results in a zero at 14.1kHz, well within the bounds of stability. Don't put high-value ceramic capacitors directly across the fast feedback inputs (FB_ to AGND) without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it's easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and FB_ pin (see the All-Ceramic-Capacitor Application section). Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there isn't enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. ( ) Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>5A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. For maximum efficiency, choose a high-side MOSFET (Q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15V). Check to ensure that the conduction losses at the minimum input voltage don't exceed the package thermal limits or violate the overall thermal budget. Check to ensure that conduction losses plus switching losses at the maximum input voltage don't exceed the package ratings or violate the overall thermal budget. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate to small package (i.e., SO-8), and is reasonably priced. Ensure that the MAX1715 DL gate driver can drive Q2; in other words, check that the gate isn't pulled up by the highside switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. Switching losses aren't an issue for the low-side MOSFET since it's a zero-voltage switched device when used in the buck topology. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case- ______________________________________________________________________________________ 19 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 power dissipation (PD) due to resistance occurs at minimum battery voltage: V 2 PD(Q1 resistance) = OUT ILOAD VIN(MIN) RDS(ON) Generally, a small high-side MOSFET is desired in order to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Again, the optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. High-side switching losses don't usually become an issue until the input is greater than approximately 15V. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2F switching loss equation. If the high-side MOSFET you've chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VIN(MAX), reconsider your choice of MOSFET. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on Q1: PD(Q1 switching) = CRSS VIN(MAX) 2 where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFETs must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Schottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency isn't critical. _________________Application Issues Dropout Performance The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. For best dropout performance, use the slowest (200kHz) ontime setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 5). Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure). Dropout design example: VIN = 3V min, VOUT = 2V, f = 300kHz. The required duty is (VOUT + VSW) / (VIN VSW) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The worstcase on-time is (VOUT + 0.075) / VIN * K = 2.075V / 3V * 3.35s-V * 90% = 2.08s. The IC duty-factor limitation is: DUTY = t ON(MIN) t ON(MIN) + t OFF(MAX) = 2.08s = 80.6% 2.08s + 500ns f ILOAD IGATE where CRSS is the reverse transfer capacitance of Q1 and IGATE is the peak gate-drive source/sink current (1A typ). For the low-side MOSFET, Q2, the worst-case power dissipation always occurs at maximum battery voltage: 1 - V 2 OUT I PD(Q2) = VIN(MAX ) LOAD RDS(ON) which meets the required duty. Remember to include inductor resistance and MOSFET on-state voltage drops (VSW) when doing worst-case dropout duty-factor calculations. The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you must "overdesign" the circuit to tolerate: ILOAD = ILIMIT(HIGH) + (LIR / 2) * ILOAD(MAX) 20 All-Ceramic-Capacitor Application Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are also expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability). In addition, their relatively low capacitance value can cause output overshoot ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 VBATT DH 1/2 MAX1715 DL PGND OUT FB R2 AGND 2V R1 FB1 0.2V FB2 VOUT OUT1 FIXED 1.8V FIXED 3.3V TO ERROR AMP1 TO ERROR FIXED AMP2 2.5V OUT2 0.2V MAX1715 Figure 8. Setting VOUT with a Resistor-Divider Figure 9. Feedback Mux when going abruptly from full-load to no-load conditions, unless there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. In some cases, there may be no room for electrolytics, creating a need for a DC-DC design that uses nothing but ceramics. The all-ceramic-capacitor application of Figure 8 replaces the standard tantalum output capacitors with ceramics. This design relies on having a minimum of 5m parasitic PC board trace resistance in series with the capacitor to reduce the ESR zero frequency. This small amount of resistance is easily obtained by locating the MAX1714A circuit 2 or 3 inches away from the CPU, and placing all the ceramic capacitors close to the CPU. Resistance values higher than 5m just improve the stability (which can be observed by examining the load-transient response characteristic as shown in the Typical Operating Characteristics). Avoid adding excess PC board trace resistance, as there's an efficiency penalty; 5m is sufficient for a 7A circuit: RESR 1 2FCOUT penalty for operating at 540kHz is about 2% to 3%, depending on the input voltage. An optional 1 resistor is placed in series with OUT. This resistor attenuates high-frequency noise in some bands, which causes double pulsing. Fixed Output Voltages The MAX1715's Dual ModeTM operation allows the selection of common voltages without requiring external components (Figure 9). Connect FB to AGND for a fixed +2.5V output or to VCC for a +3.3V output, or connect FB directly to OUT for a fixed +1.0V output. Setting VOUT with a Resistor-Divider The output voltage can be adjusted with a resistordivider if desired (Figure 8). The equation for adjusting the output voltage is: R1 VOUT = VFB 1 + R2 where VFB is 1.0V and R2 is about 10k. Two-Stage (5V-Powered) Notebook CPU Buck Regulator The most efficient and overall cost-effective solution for stepping down a high-voltage battery to a very low output voltage is to use a single-stage buck regulator that's powered directly from the battery. However, there may be situations where the battery bus can't be routed near the CPU, or where space constraints dictate the smallest possible local DC-DC converter. In such cases, the 5V-powered circuit of Figure 10 may be appropriate. The reduced input voltage allows a higher Output overshoot (V) determines the minimum output capacitance requirement. In this example, the switching frequency has been increased to 600kHz and the inductor value has been reduced to 0.5H (compared to 300kHz and 2H for the standard 8A circuit) to minimize the energy transferred from inductor to capacitor during load-step recovery. The overshoot must be calculated to avoid tripping the OVP latch. The efficiency Dual Mode is a trademark of Maxim Integrated Products. ______________________________________________________________________________________ 21 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 1F 20 1F VIN 4.5V TO 5.5V C1 4 x 10F/25V ILIM VCC ON/OFF ON2 V+ VDD BST2 DH2 0.1F IRF7805 VOUT 2.5V AT 7A C2 3 x 470F KEMET T510 L1 0.5H MAX1715 0.22F REF LX2 DL2 PGND IRF7805 VCC 100k PGOOD TON FB2 OUT2 AGND SKIP Figure 10. 5V-Powered, 8A CPU Buck Regulator switching frequency and a much smaller inductor value. PC Board Layout Guidelines Careful PC board layout is critical to achieving low switching losses and clean, stable operation. This is especially true for dual converters, where one channel can affect the other. The switching power stages require particular attention (Figure 11). Refer to the MAX1715 EV kit data sheet for a specific layout example. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. Run the power plane ground currents on the top side only, if possible. * Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2. 22 * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Tie AGND and PGND together close to the IC. Do not connect them together anywhere else. Carefully follow the grounding instructions under Step 4 of the Layout Procedure. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. * LX_ and PGND connections to the synchronous rectifiers for current limiting must be made using Kelvin sense connections to guarantee the current-limit accuracy. With SO-8 MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while tying in PGND and LX_ inside (underneath) the SO-8 package. * When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. * Ensure that the OUT connection to COUT is short and direct. However, in some cases it may be desirable to deliberately introduce some trace length between the OUT inductor node and the output filter capacitor (see the All-Ceramic-Capacitor Application section). * Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, ILIM, FB). Use PGND1 and PGND2 as EMI shields to keep radiated switching noise away from the IC, feedback dividers, and analog bypass capacitors. * Make all pin-strap control input connections (SKIP, ILIM, etc.) to AGND or VCC rather than PGND_or VDD. 4) Make the DC-DC controller ground connections as follows: near the IC, create a small analog ground plane. Connect this plane to AGND and use this plane for the ground connection for the REF and VCC bypass capacitors, FB dividers, and ILIM resistors (if any). Create another small ground island for PGND, and use it for the V DD bypass capacitor, placed very close to the IC. Connect the AGND and the PGND pins together under the IC (this is the only connection between AGND and PGND). 5) On the board's top side (power planes), make a star ground to minimize crosstalk between the two sides. The top-side star ground is a star connection of the input capacitors, side 1 low-side MOSFET, and side 2 low-side MOSFET. Keep the resistance low between the star ground and the source of the lowside MOSFETs for accurate current limit. Connect the top-side star ground (used for MOSFET, input, and output capacitors) to the small PGND island with a short, wide connection (preferably just a via). If multiple layers are available (highly recommended), create PGND1 and PGND2 islands on the layer just below the top-side layer (refer to the MAX1715 EV kit for an example) to act as an EMI shield. Connect each of these individually to the star ground via, which connects the top side to the PGND plane. Add one more solid ground plane under the IC to act as an additional shield, and also connect that to the star ground via. 6) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. MAX1715 Layout Procedure 1) Place the power components first, with ground terminals adjacent (Q2 source, CIN-, COUT-, D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the synchronous rectifiers MOSFETs, preferably on the back side in order to keep LX_, PGND_, and the DL_ gate-drive line short and wide. The DL_ gate trace must be short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the MOSFET is 1 inch from the controller IC). 3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. USE AGND PLANE TO: USE PGND PLANE TO: - BYPASS VCC AND REF - BYPASS VDD - CONNECT PGND TO THE TOPSIDE STAR GROUND - TERMINATE EXTERNAL FB DIVIDER (IF USED) OUT1 - TERMINATE RILIM (IF USED) AGND VIA TO OUT1 - PIN-STRAP CONTROL INPUTS PGND L1 VIA TO PGND GROUND C3 C4 VIA TO OUT2 OUT2 D2 L2 D1 N1 C1 C2 N2 VIA TO GROUND VIA TO LX1 NOTE: EXAMPLE SHOWN IS FOR DUAL N-CHANNEL MOSFET. VIN VIA TO LX2 CONNECT PGND TO AGND BENEATH THE MAX1715 AT ONE POINT ONLY AS SHOWN. Figure 11. PC Board Layout Example ______________________________________________________________________________________ 23 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 Pin Configuration TOP VIEW OUT1 1 FB1 2 ILIM1 3 V+ 4 TON 5 SKIP 6 PGOOD 7 AGND 8 REF 9 ON1 10 ON2 11 ILIM2 12 FB2 13 OUT2 14 28 N.C. 27 LX1 26 DH1 25 BST1 24 DL1 MAX1715 23 N.C. 22 PGND 21 VCC 20 VDD 19 DL2 18 BST2 17 DH2 16 LX2 15 N.C. QSOP 24 ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers Package Information QSOP.EPS MAX1715 ______________________________________________________________________________________ 25 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 NOTES 26 ______________________________________________________________________________________ Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 NOTES ______________________________________________________________________________________ 27 Ultra-High Efficiency, Dual Step-Down Controller for Notebook Computers MAX1715 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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